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ltc6909 1 6909f 1 to 8 output, multiphase silicon oscillator with spread spectrum modulation the ltc ? 6909 is an easy to use precision oscillator that can provide 1-, 2-, 3-, 4-, 5-, 6-, 7- or 8-phase synchro- nized outputs. the ltc6909 also offers spread spectrum frequency modulation (ssfm), which can be enabled to improve electromagnetic compatibility (emc) perfor- mance. eight separate outputs provide up to eight rail-to-rail, 50% duty cycle clock signals. using three logic inputs, the outputs are con? gured for phase separation, ranging from 45 to 120 (three to eight phases). the clock outputs can also be held low or con? gured for hi-z. a single resistor, combined with the phase con? guration, sets the output frequency, based on the following formula: f out = 20mhz ? 10k/(r set ? ph) where ph = 3, 4, 5, 6, 7 or 8 the ltc6909 can be used in applications requiring only one or two output phases. alternatively, the ltc6908 family of parts provides the same two output signals but in a smaller sot-23 or 2mm 3mm dfn package. the ltc6908-1 provides complimentary (180) outputs while the ltc6908-2 provides quadrature (90) outputs. synchronizing multiple switching power supplies 1-, 2-, 3-, 4-, 5-, 6-, 7- or 8-phase outputs one external resistor sets the output frequency from 12.5khz to 6.67mhz optional spread spectrum frequency for improved emi performance 10% frequency spreading outputs can be held low or floated (hi-z) three spread spectrum modulation rates f out /16, f out /32 and f out /64 400a supply current operates from a single 2.7v to 5.5v supply fast start-up time first cycle accurate outputs are high impedance until frequency settles ms16 package typical application features applications description providing a 4-phase synchronizing clock to ltm modules l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6342817, 6614313, 7417509. ltc6909 10v to 14v 0.1f 71.5k 0.1f 0.01f enable ssfm disable ssfm ltm4601 intv cc ltm4601-1 ltm4601-1 ltm4601-1 tracking s0ft-start 1.5v 48a tracking tracking 6909 ta01 v + d gnd v + a set ph0 ph1 ph2 mod out1 out2 out3 out4 out5 out6 out7 out8 frequency (fundamental and harmonics shown) 150khz output (dbc) output (dbc) C20 C10 0 6909 ta01b C30 C40 C50 30mhz C20 C10 0 C30 C40 C50 ssfm disabled ssfm enabled ssfm = f out /32 150khz to 30mhz output frequency spectrum (9khz res bw)
ltc6909 2 6909f supply voltage (v + a) to gnd ......................................6v supply voltage (v + d) to gnd ......................................6v maximum voltage on any pin ................ (gnd C 0.3v) v pin (v + + 0.3v) operating temperature range (note 2) ltc6909c ............................................ C40c to 85c ltc6909i.............................................. C40c to 85c ltc6909h .......................................... C40c to 125c speci? ed temperature range (note 3) ltc6909c ................................................ 0c to 70c ltc6909i.............................................. C40c to 85c ltc6909h .......................................... C40c to 125c junction temperature ........................................... 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c or as noted. test conditions are v + = v + a = v + d = 2.7v to 5.5v, r l = 5k, c l = 5pf unless otherwise noted. the modulation is turned off (mod is connected to out1) and ph = 8 unless otherwise speci? ed. r set is de? ned as the resistor connected from the set pin to the v + a pin. symbol parameter conditions min typ max units f master frequency accuracy (notes 4, 5) v + = 5v ph = 3 500khz f master 10mhz 500khz f master 10mhz 100khz f master < 500khz 10mhz f master 20mhz 1 2.5 3 3.5 2.5 3 4.5 3.5 % % % % v + = 2.7v ph = 3 500khz f master 10mhz 500khz f master 10mhz 100khz f master < 500khz 0.5 2 2.5 2.5 3 4.5 % % % f out / t frequency drift over temperature r set = 100k 0.004 %/c f out / v + frequency drift over supply v + = 4.5v to 5.5v, r set = 100k v + = 2.7v to 3.6v, r set = 100k 0.4 0.04 0.9 0.35 %/v %/v pin configuration absolute maximum ratings electrical characteristics lead free finish tape and reel part marking* package description specified temperature range ltc6909cms#pbf ltc6909cms#trpbf 6909 16-lead plastic msop 0c to 70c ltc6909ims#pbf ltc6909ims#trpbf 6909 16-lead plastic msop C40c to 85c ltc6909hms#pbf ltc6909hms#trpbf 6909 16-lead plastic msop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a la bel on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ order information 1 2 3 4 5 6 7 8 v + a gnd ph0 ph1 out1 out2 out3 out4 16 15 14 13 12 11 10 9 set ph2 mod v + d out8 out7 out6 out5 top view ms package 16-lead plastic msop t jmax = 150c, ja = 125c/w
ltc6909 3 6909f symbol parameter conditions min typ max units r set range of the r set resistor connected between the v + a pin and the set pin 4.5v v + 5.5v 2.7v v + 4.5v 10 20 2000 2000 k k frequency spread with ssfm enabled r set = 100k mod pin = v + , gnd or open 7 10 13 % long-term stability of the output frequency (note 9) 300 ppm/ khr duty cycle (note 6) ssfm disabled 45 50 55 % v + a, v + d operating supply voltage range 2.7 5.5 v i s v + combined supply current r set = 2m, r l = , ph = 8, mod = v + , (f out = 12.5khz), ssfm = f out /64 v + = 5v v + = 2.7v 0.6 0.55 0.85 0.8 ma ma r set = 20k, r l = , ph = 3, mod = gnd, (f out = 3.33mhz), ssfm = f out /16 v + = 5v v + = 2.7v 2.4 1.55 2.7 1.8 ma ma r set = 2m, r l = , ph = 8, mod = out1, (f out = 12.5khz), ssfm off v + = 5v v + = 2.7v 0.4 0.37 0.65 0.6 ma ma v ih_mod high level mod input voltage v + C 0.4 v v il_mod low level mod input voltage 0.4 v i mod mod input current (note 7) mod pin = v + , v + = 5v mod pin = gnd, v + = 5v C4 2 C2 4a a v ih_ph high level phx input voltage phx refers to ph0, ph1 and ph2 v + C 0.4 v v il_ph low level phx input voltage phx refers to ph0, ph1 and ph2 0.4 v i in_phx digital input current, ph0, ph1, ph2 0v < v in < v + 1 a v oh high level output voltage (out1 through out8)(note 7) v + = 5v no load 5ma load to gnd 4.35 4.92 4.65 v v v + = 2.7v no load 3ma load to gnd 2.1 2.63 2.4 v v v ol low level output voltage (out1 through out8)(note 7) v + = 5v no load 5ma load to v + 0.07 0.25 0.55 v v v + = 2.7v no load 3ma load to v + 0.07 0.25 0.55 v v t r output rise time (note 8) v + = 5v v + = 2.7v 1.6 2.5 ns ns t f output fall time (note 8) v + = 5v v + = 2.7v 1.6 2 ns ns the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c or as noted. test conditions are v + = v + a = v + d = 2.7v to 5.5v, r l = 5k, c l = 5pf unless otherwise noted. the modulation is turned off (mod is connected to out1) and ph = 8 unless otherwise speci? ed. r set is de? ned as the resistor connected from the set pin to the v + a pin. electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: ltc6909c and the ltc6909i are guaranteed functional over the operating temperature range of C40c to 85c. note 3: the ltc6909c is guaranteed to meet speci? ed performance from 0c to 70c. the ltc6909c is designed, characterized and expected to meet speci? ed performance from C40c to 85c but is not tested or qa sampled at these temperatures. the ltc6909i is guaranteed to meet speci? ed performance from C40c to 85c. the ltc6909h is guaranteed to meet speci? ed performance from C40c to 125c.
ltc6909 4 6909f frequency error vs r set , v + = 2.7v frequency error vs r set , v + = 5v frequency error vs temperature supply current vs supply voltage supply current vs r set (ssfm enabled) supply current vs r set (ssfm disabled) note 4: f master is the internal master oscillator frequency. the output frequency is f master /ph. the ph value is determined by the connections of the ph0, ph1 and ph2 pins as described in the applications information section. note 5: frequency accuracy is de? ned as the deviation from the f out equation. f master = 20mhz ? 10k/r set , f out = 20mhz ? 10k/(r set ? ph), ph = 3, 4, 5, 6, 7 or 8. note 6: guaranteed by 5v test. note 7: to conform to the logic ic standard, current out of a pin is de? ned as a negative value. note 8: output rise and fall times are measured between the 10% and the 90% power supply levels with no output loading. these speci? cations are based on characterization. electrical characteristics typical performance characteristics note 9: long term drift on silicon oscillators is primarily due to the movement of ions and impurities within the silicon and is tested at 30c under otherwise nominal operating conditions. long term drift is speci? ed as ppm/ khr due to the typically nonlinear nature of the drift. to calculate drift for a set time period, translate that time into thousands of hours, take the square root and multiply by the typical drift number. for instance, a year is 8.77khr and would yield a drift of 888ppm at 300ppm/ khr . drift without power applied to the device (aging) may be approximated as 1/10th of the drift with power, or 30ppm/ khr for a 300ppm/ khr device. supply voltage (v) 2.7 0 supply current (a) 200 600 800 1000 3.7 4.7 1800 6909 g04 400 3.2 4.2 1200 1400 1600 r set = 2m r set = 20k r set = 100k r set = 400k ph = 3, ssfm enabled c load = 5pf r load = 5k r set () 10k 0 i supply (a) 1000 2000 3000 500 1500 2500 100k 1m 10m 6909 g05 c load = 5pf v + = 5v, ph = 3 v + = 5v, ph = 8 v + = 2.7v, ph = 3 v + = 2.7v, ph = 8 r set () 10k 0 i supply (a) 1000 2000 3000 500 1500 2500 100k 1m 10m 6909 g06 c load = 5pf r load = 5k v + = 5v, ph = 3 v + = 5v, ph = 8 v + = 2.7v, ph = 3 v + = 2.7v, ph = 8 r set () 10k frequency error (%) 5 4 3 2 1 0 C1 C2 C3 C4 C5 100k 1m 10m 6909 g01 t a = 25c typical max guaranteed min over temperature typical min guaranteed max over temperature r set () 10k frequency error (%) 5 4 3 2 1 0 C1 C2 C3 C4 C5 100k 1m 10m 6909 g02 t a = 25c typical max guaranteed max over temperature guaranteed min over temperature typical min temperature (c) C 40 frequency error (%) 20 60 6909 g03 C 20 0 40 1.00 0.75 0.50 0.25 0 C 0.25 C 0.50 C 0.75 C 1.00 80 typical max typical min
ltc6909 5 6909f supply current vs temperature typical output resistance vs supply voltage output rise/fall time vs supply voltage typical performance characteristics jitter vs r set output operating at 3.33mhz output operating at 6.66mhz output frequency spectrum ssfm enable and disabled supply voltage (v) 3 20 output resistance () 30 50 60 70 4.2 4.4 4.6 4.8 110 6909 g08 40 3.2 2.8 3.4 3.6 3.8 4 5 80 90 100 r set () 10k 0 jitter (% p-p) 0.4 0.8 1.2 0.2 0.6 1.0 100k 1m 10m 6909 g10 c load = 5pf v + = 2.7v, div = 8 v + = 5v, div = 8 v + = 5v, div = 3 v + = 2.7v, div = 3 C100 0 2.5 mhz 10db/div frequency (200khz/div) 6909 g13 res bw = 9khz ssfm disabled ssfm enabled (n = 16) supply voltage (v) output rise/fall time (ns) 6909 g09 2.7 3.2 3.7 4.2 4.7 5.2 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 fall time rise time c load = 5pf t a = 25c r load = 5k 500mv/div 50ns/div v + = 3.3v c load = 15pf r load = 5k 6909 g11 1v/div 50ns/div v + = 5v c load = 15pf r load = 5k 6909 g12 temperature (c) C20 400 supply current (a) 450 500 550 60 80 100 700 6909 g07 C40 0 20 40 120 600 650 v + = 2.7v v + = 5v r set = 100k ph = 3 c load = 5pf ssfm disabled
ltc6909 6 6909f v + a (pin 1): analog voltage supply (2.7v v + a 5.5v). this supply should be kept free of noise and ripple. it should be bypassed directly to gnd with a 0.1f or greater low esr capacitor. v + a and v + d must be connected to the same supply voltage. gnd (pin 2): ground connections. should be tied to a ground plane for best performance. ph0, ph1, ph2 (pins 3, 4, 15): output phasing selec- tion pins. these are standard cmos logic input pins and they do not have an internal pull-up or pull-down. these pins must be connected to a valid logic input 0 or 1 volt- age. connect the pins to gnd for a logic 0 and to the v + d pin for a logic 1. these pins con? gure the output phase relationships as follows: ph2 ph1 ph0 mode 0 0 0 all outputs are floating (hi-z) 0 0 1 all outputs are held low 0 1 0 3-phase mode (ph = 3) 0 1 1 4-phase mode (ph = 4) 1 0 0 5-phase mode (ph = 5) 1 0 1 6-phase mode (ph = 6) 1 1 0 7-phase mode (ph = 7) 1 1 1 8-phase mode (ph = 8) the ph0, ph1, ph2 pin connections not only determine the phase relationship of the output signals but also divide the master oscillator frequency by the value ph. out1 through out8 (pins 5 through 12): oscillator outputs. these are cmos rail-to-rail logic outputs with a series resistance of approximately 40, capable of driving 1k and/or 50pf loads. larger loads may cause minor frequency inaccuracies due to supply bounce at high frequencies. when any output pin is not in use, it is in a ? oating, high impedance state. the outputs are also held in a high impedance state during start-up. after the parts internal frequency setting loop has settled, the outputs are active, clean and operating at the set frequency (? rst cycle accurate). v + d (pin 13): digital voltage supply (2.7v v + d 5.5v). this pin should be bypassed directly to gnd with a 0.1f or greater low esr capacitor. v + d and v + a must be con- nected to the same supply voltage. mod (pin 14): spread spectrum frequency modulation setting input. this input selects among four modulation rate settings. the mod pin should be tied to ground for an f out /16 modulation rate. floating the mod pin selects an f out /32 modulation rate. the mod pin should be tied to v + d for the f out /64 modulation rate. tying one of the active outputs to the mod pin turns the modulation off. to detect a ? oating mod pin, the ltc6909 attempts to pull the pin to the midsupply point. this is realized with two internal current sources, one tied to v + d and mod and the other one tied to gnd and mod. therefore, driv- ing the mod pin high requires sourcing approximately 2a. likewise, driving the mod pin low requires sinking approximately 2a. when the mod pin is ? oated for the f out /32 modulation rate, it must be bypassed using a 1nf or larger, capacitor to gnd. any ac signal coupling to the mod pin could potentially be detected and stop the frequency modulation. set (pin 16): frequency setting resistor input. the value of the resistor connected between this pin and v + a deter- mines the frequency of the master oscillator. the output frequency, f out , is the master oscillator frequency divided by ph as set by the ph0, ph1 and ph2 pin connections. the voltage on this pin is held approximately 1.1v below v + a. for best performance, use a precision metal ? lm resistor with a value between 20k and 400k, and limit the capacitance on the pin to less than 10pf. resistor values outside of this range will have some loss of accuracy as noted in the electrical characteristics table. pin functions
ltc6909 7 6909f block diagram out1 6909 bd v + a set 16 mod 5 out2 6 out3 7 out4 8 out5 9 out6 10 out7 11 out8 12 1 output phasing drivers por ph0 ph1 ph2 v + d (ssfm = off) 3-state input decoder when a clock signal is present at the mod pin input, the modulation is disabled pseudorandom code generator C + f master = 20mhz ? 10k ? = 20mhz ? 10k/r set v + C v set master oscillator i master i master i ref mdac v bias r set v set out v v + gnd 14 gnd 2 + C + C i set = r set v + C v set 3 4 15 13 driver driver driver driver driver driver driver driver output hi-z until stable divide by 16/32/64 detect clock input 1 pole lpf
ltc6909 8 6909f i res (a) v res = v + C v set 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.1 10 100 1000 6909 f01 1 v + = 5v v + = 3v t a = 25c as shown in the block diagram, the ltc6909s master oscillator is controlled by th e ratio of the voltage between the v + a and set pins and the current entering the set pin (i master ). when the spread spectrum frequency modula- tion (ssfm) is disabled, i master is strictly determined by the (v + a C v set ) voltage and the r set resistor. when ssfm is enabled, i master is modulated by a ? ltered pseu- dorandom noise (prn) signal. here the i master current is a random value uniformly distributed between (i set C 10%) and (i set + 10%). in this way, the frequency is modulated to produce an approximately ? at frequency spectrum, centered about the set frequency with a bandwidth equal to approximately 20% of the center frequency. the voltage on the set pin is forced to approximately 1.1v below v + a by the pmos transistor and its gate bias voltage. this voltage is accurate to 5% at a particular input current and supply voltage (see figure 1). the ltc6909 is optimized for use with resistors between 20k and 400k corresponding to master oscillator frequencies between 500khz and 10mhz. accurate master oscillator frequencies up to 20mhz (r set = 10k) are attainable if the supply voltage is greater than 4v. the r set resistor, connected between the v + a and set pins, locks together the (v + a C v set ) voltage and the current i set . this allows the parts to attain excellent frequency accuracy regardless of the precision of the set pin. the master oscillation frequency is: f master = 20mhz ? 10k/r set figure 1. v + C v set variation with i res when the spread spectrum frequency modulation (ssfm) is disabled, the master oscillator frequency is stationary. when ssfm is enabled, the master oscillator frequency varies from 0.9 ? f master to 1.1 ? f master . output frequency and con? gurations the output frequency of the ltc6909 is set by the r set resistor value and the connections of the ph0, ph1 and ph2 logic input pins. the following formula de? nes the relationship: f out = 20mhz ? 10k/(r set ? ph) where ph = 3, 4, 5, 6, 7 or 8 and is de? ned as follows: ph2 ph1 ph0 mode 0 0 0 all outputs are floating (hi-z) 0 0 1 all outputs are held low 0 1 0 3-phase mode (ph = 3) 0 1 1 4-phase mode (ph = 4) 1 0 0 5-phase mode (ph = 5) 1 0 1 6-phase mode (ph = 6) 1 1 0 7-phase mode (ph = 7) 1 1 1 8-phase mode (ph = 8) the ph0, ph1 and ph2 pins are standard logic input pins. these pins do not have any active pull-up or pull-down circui tr y. a s such, they c annot be le f t ? oating and must be connected to a valid logic high or low voltage. the ph0, ph1 and ph2 pin connections not only divide the master oscillator frequency by the value ph but also determine the phase relationship between the output signals. figure 2 shows the output waveforms for each of the eight pos- sible output con? gurations. note that 2-phase, complementary (180 phase shifted) outputs are available in the 4-, 6- and 8-phase modes by choosing the correct pair of signals. for example, in 4-phase mode, out1 and out3 (or out2 and out4) are complementary. operation
ltc6909 9 6909f operation figure 2a. output waveforms for different ph settings master oscillator out1 out2 out3 out4 hi-z out5 hi-z out6 hi-z out7 hi-z out8 hi-z out1 out2 out3 out4 out5 hi-z out6 hi-z out7 hi-z out8 hi-z out1 out2 out3 out4 out5 out6 hi-z out7 hi-z out8 hi-z out1 out2 out3 out4 out5 out6 out7 hi-z out8 hi-z 6909 f02a ph2 - ph1 - ph0 = 000 all outputs are hi-z ph2 - ph1 - ph0 = 001 all outputs are low ph2 - ph1 - ph0 = 010 ph = 3, f output = f master /3 adjacent outputs are phase shifted by 120 ph2 - ph1 - ph0 = 011 ph = 4, f output = f master /4 adjacent outputs are phase shifted by 90 ph2 - ph1 - ph0 = 100 ph = 5, f output = f master /5 adjacent outputs are phase shifted by 72 ph2 - ph1 - ph0 = 101 ph = 6, f output = f master /6 adjacent outputs are phase shifted by 60
ltc6909 10 6909f figure 2b. output waveforms for different ph settings operation out1 out2 out3 out4 out5 out6 out7 out8 hi-z out1 out2 out3 out4 out5 out6 out7 out8 6909 f02b ph2 - ph1 - ph0 = 110 ph = 7, f output = f master /7 adjacent outputs are phase shifted by 51.43 ph2 - ph1 - ph0 = 111 ph = 8, f output = f master /8 adjacent outputs are phase shifted by 45 master oscillator
ltc6909 11 6909f spread spectrum frequency modulation the ltc6909 can operate with spread spectrum frequency modulation (ssfm). in this mode, the oscillators frequency is modulated by a pseudorandom noise (prn) signal to spread the oscillators energy over a wide frequency band. this spreading decreases the peak electromagnetic radiation levels and improves electromanetic compatibility (emc) performance. the amount of frequency spreading is ? xed at 20% (10%), where frequency spreading is de? ned as: frequency spreading (in %) = 100 ? (f max C f min )/f out the i master current is a dynamic signal generated by a multiplying digital-to-analog converter (mdac) refer- enced to i set and lowpass ? ltered. i master varies in a psuedorandom noise-like manner between 0.9 ? i set and 1.1 ? i set . this causes the output frequency to vary in a pseudorandom noise-like manner between 0.9 ? f out and 1.1 f out . to disable the ssfm, connect one of the active outputs to the mod pin. an ac detector circuit shuts down the modulation circuitry if a frequency in the vicinity of the output frequency is detected at the mod pin. as stated previously, the modulating waveform is a pseu- dorandom noise-like waveform. the pseudorandom signal is generated by a linear feedback shift register that is 15 bits long. the pseudorandom sequence will repeat every (2 15 C 1) ? n clock cycles. this guarantees a repetition rate below 13hz for output frequencies up to 6.67mhz. seven bits of the shift register are sent in parallel to the mdac which produces the modulating current waveform. being a digitally generated signal, the output of the mdac is not a perfectly smooth waveform, but consists of (2 7 ) discrete steps that change every shift register clock cycle. note that the shift register clock is the output frequency, f out , divided by n, where n is the modulation rate divider setting, which is determined by the state of the mod pin. the mod pin should be tied to ground for the n = 16 set- ting. floating the mod pin selects n = 32. the mod pin should be tied to v + for the n = 64 setting. the output of the mdac is then ? ltered by a lowpass ? lter with a corner frequency set to the modulation rate (f out /n). this limits the rate of frequency change and softens the corners of the frequency control signal, but allows the waveform to fully settle at each frequency step. the rise and fall times of this single pole ? lter are approximately 0.35/f corner . this is bene? cial for clocking switching regulators, as discussed in the applications information section. figure 3 illustrates how the output frequency varies over time. figure 3 operation t repeat = ((2 15 C 1) ? n)/f out t step = n/f out f out + 10% 128 steps t repeat t step f out C 10% time frequency 6909 f03
ltc6909 12 6909f selecting the frequency-setting resistor the ltc6909 has a master oscillator frequency range spanning 100khz to 20mhz depending on the r set resis- tor value. however, accuracy may suffer if the oscillator is operated at a master oscillator frequency greater than 10mhz with a supply voltage lower than 4v. with a linear correspondence between the master oscillator period and the r set resistance, a simple equation relates resistance with frequency. r set =10k ? 20mhz/f master r setmin = 10k (5v supply), 20k (2.7v supply), r setmax = 2m any r set resistor tolerance will shift the output frequency by the same amount. alternative methods of setting the output frequency of the ltc6909 the oscillator may be programmed by any method that sources a current into the set pin. the circuit in figure 4 sets the oscillator frequency using a programmable cur- rent source and in the expression for f out , the resistor r set is replaced by the ratio of 1.1v/i control . as already explained in the operation section, the voltage difference between v + and set is approximately 1.1v 5%, there- fore, the figure 4 circuit is less accurate than if a resistor controls the output frequency. figure 4. current controlled oscillator figure 5 shows the ltc6909 con? gured as a v co . a volt- age source is connected in series with an external 10k resistor. the master oscillator frequency, f master , will vary with v control , that is the voltage source connected between v + and the set pin. again, this circuit decouples figure 5. voltage controlled oscillator the relationship between the input current and the volt- age between v + and set; the frequency accuracy will be degraded. the oscillator frequency, however, will increase monotonically with decreasing v control . setting the modulation rate of the ltc6909 the modulation rate of the ltc6909 is equal to f out /n, where n is the modulation rate divider setting, which is determined by the state of the mod pin. the mod pin should be tied to ground for the n = 16 setting. floating the mod pin selects n = 32. the mod pin should be tied to v + for the n = 64 setting. to disable the ssfm, connect one of the active outputs to the mod pin. an ac detector circuit shuts down the modulation circuitry if a frequency that is close to the output frequency is detected at the mod pin. when the mod pin is ? oated, for the f out /32 modulation rate, it must be bypassed by at least a 1nf capacitor to gnd . any ac signal coupling to the mod pin could poten- tially be detected and stop the frequency modulation. driving logic circuits the outputs of the ltc6909 are suitable for driving gen- eral digital logic circuits. however, the form of frequency spreading used in the ltc6909 may not be suitable for many logic designs. many logic designs have fairly tight timing and cycle-to-cycle jitter requirements. these sys- tems often bene? t from a spread spectrum clocking system where the frequency is slowly and linearly modulated by a triangular waveform, not a pseudorandom waveform. this type of frequency spreading maintains a minimal difference in the timing from one clock edge to the next adjacent clock edge (cycle-to-cycle jitter). the ltc6909 uses a c byp i control f master = 10k ? (20mhz/1.13v) ? i control (a) v + a v + gnd set 6909 f04 c byp v control f out = 10k ? 20mhz/ r set (1 C v control /1.13v) v + a v + gnd set 6909 f05 r set + C applications information
ltc6909 13 6909f pseudorandom modulating signal where the frequency transitions have been slowed and the corners rounded by a ? rst order lowpass ? lter with a corner frequency set to the modulation rate (f out /n), where n is the modulation rate divider setting, which is determined by the state of the mod pin. this ? ltered modulating signal may be ac- ceptable for many logic systems but the cycle-to-cycle jitter issues must be considered carefully. driving switching regulators the ltc6909 is designed primarily to provide an accurate and stable clock for switching regulator systems. the cmos logic outputs are suitable for directly driving most switching regulators and switching controllers. linear technology has a broad line of fully integrated switching regulators and switching regulator controllers designed for synchronization to an external clock. all of these parts have one pin assigned for external clock input. the nomenclature varies depending on the parts family his- tory. sync, pllin, sync/mode, extclk, fcb and s/s (shorthand for sync/shdn) are examples of clock input pin names used with linear technology ics. for the best emc performance, the ltc6909 should be run with the mod pin tied to ground (ssfm enabled, modula- tion rate set to f out /16). regulatory testing is done with strictly speci? ed bandwidths and conditions. modulating faster than, or as close to, the test bandwidth as possible gives the lowest readings. the optimal modulating rate is not as straightforward when the goal is to lower radiated signal levels interfering with other circuitry in the system. the modulation rate will have to be evaluated with the speci? c system conditions to determine the optimal rate. depending on the speci? c frequency synchronization method a switching regulator employs, the modulation rate must be within the synchronization capability of the regulator. many regulators use a phase-locked loop (pll) for synchronization. for these parts, the pll loop ? lter should be designed to have suf? cient capture range and bandwidth. the frequency hopping transitions of the ltc6909 are slowed by a lowpass ? lter. the corner frequency of this ? lter is set to the modulation rate (f out /n), where n is the modulation rate divider setting, which is determined by the state of the mod pin. the mod pin should be tied to ground for the n = 16 setting. floating the mod pin selects n = 32. the mod pin should be tied to v + for the n = 64 setting. this is an important feature when driving a switching regulator. the switching regulator is itself a servo loop with a bandwidth typically on the order of 1/10 to 1/20 of the operating frequency. when the clock frequencys transition is within the bandwidth of the switch- ing regulator, the regulators output stays in regulation. if the transition is too sharp, beyond the bandwidth of the switching regulator, the regulators output will experience a sharp jump and then settle back into regulation. if the bandwidth of the regulator is suf? ciently high, beyond f out /n, then there will not be any regulation issues. one aspect of the output voltage that will change is the output ripple voltage. every switching regulator has some output ripple at the clock frequency. for most switching regulator designs with ? xed mosfets, ? xed inductor, ? xed capacitors, the amount of ripple will vary with the regulators operating frequency (the main exception be- ing hysteretic architecture regulators). an increase in frequency results in lower ripple and a frequency decrease gives more ripple. this is true for static frequencies or dynamic frequency modulated systems. if the modulating signal was a triangle wave, the regulators output would have a ripple that is amplitude modulated by the triangle wave. this repetitive signal on the power supply could cause system problems by mixing with other desired signals creating distortion. depending on the switching regulators inductor design and triangle wave frequency, it may even result in an audible noise. the ltc6909 uses a pseudorandom noise-like signal. on an oscilloscope, it looks essentially noise-like of even amplitude. the signal is broadband and any mixing issues are eliminated. ad- ditionally, the pseudorandom signal repeats at such a low rate that it is well below the audible range. the ltc6909 with the spread spectrum frequency modu- lation enabled results in improved emc performance. if the bandwidth of the switching regulator is suf? cient, not a dif? cult requirement in most cases, the regulators regulation, ef? ciency and load response are maintained applications information
ltc6909 14 6909f while peak electromagnetic radiation (or conduction) is reduced. output ripple may be somewhat increased, but its behavior is very much like noise and its system impact is benign. supply bypassing, signal connections and pcb layout using the ltc6909 in spread spectrum mode naturally eliminates any concerns for output frequency accuracy and stability as it is continually hopping to new settings. in ? xed frequency applications however, some attention to v + supply voltage ripple is required to minimize additional output frequency error. ripple frequency components on the supply line near the programmed output frequency of the ltc6909 in excess of 30mv p-p could create an addi- t i o n a l 0 . 2 % o f f r e q u e n c y e r r o r. i n a p p l i c a t i o n s w h e r e a ? x e d frequency ltc6909 output clock is used to synchronize the same switching regulator that provides the v + supply to the oscillator, noticeable jitter of the clock may occur if the ripple exceeds 30mv p-p . the ltc6909s accuracy is affected as described above by supply ripple on the v + a pin only. the v + d pin is es- sentially insensitive to supply ripple. the v + a pin supplies the power for the analog section of the ltc6909 and its current is largely constant for a given r set resistor value. the v + d pin supplies the digital section including the output drivers and its current requirement consists mainly of large bursts that digital circuitry requires when switching. the peak current required by the output drivers is by far the largest. the current is mainly dependent on output capacitive loading and the supply voltage. figure 6 shows how to connect the v + a and v + d supply pins to the power supply as well as a suggested pcb layout. the pcb layout assumes a two layer board with a ground plane in the layer beneath the part and 0805 sized passive components. the pcb layout in figure 6 is a guide and need not be followed exactly. however, there are several items to note from the layout as follows: 1. there should be a ground plane underneath and around the part. connect the gnd pi n to this plane through multiple (three to four minimum) vias to minimize inductance. 2. place the bypass capacitors, c1 and c2, as close to the v + a and v + d p i n s a s p o s s i b l e t o m i n i m i z e t h e i n d u c t a n c e between the capacitors lead and the parts pins. 3. the connection to the v + a and v + d pins to the main supply should be through a low impedance path. if the board has a v + power plane, use it instead of the top layer connection shown in figure 6. use multiple vias (three to four minimum) at each point to connect the v + a and v + d pins to the v + plane to minimize the inductance. 4. connect the bypass capacitors, c1 and c2, directly to the gnd pin using a low inductance path. the connection from c1 to the gnd pin is easily done directly on the top layer. the c2 path is more dif ? cult but is accomplished through multiple vias to the ground plane. 5. connect the r set resistor directly to the set pin and the v + a pin. connecting the resistor to the v + supply through any manner other than directly to the v + a pin will result greater frequency error. 6. provide a ground shield around the r set resistor and its connections to v + a and set. the set pin is a fairly high impedance point and is susceptible to interference from noisy signal lines such as the parts cmos outputs out1 through out8. 7. route the output signals, out1 through out8, away from the set pin as soon as possible to minimize coupling. 8. when using the ltc6909 with spread spectrum disabled, an active output is connected to the mod pin. this is best done by routing the out1 signal under the part as shown in figure 6. the ground shield between this trace and the r set r e s i s t o r i s v e r y i m p o r t a n t t o m i n i m i z e coupling of the out1 signal into the set pin. applications information
ltc6909 15 6909f figure 7. start-up time figure 6. supply bypassing and pcb layout 9. the connections for ph0, ph1 and ph2 are not shown in figure 6. these pins are connected to either gnd or v + d depending on the output phasing required for the application. connection to ground is done underneath the part. connecting ph2 to v + d is also straightforward. connecting ph0 or ph1 to v + d may require one or both traces to go down a layer. if you are dynamically changing one or all of the ph pins, place a 10k resis- tor in series with the signal line. locate the resistor fairly close to the ph pin. this signal typically comes from a microcontroller or the power good signal from a switching regulator and is usually quite noisy. the series resistor provides some isolation between the noisy signal and the ltc6909. start-up issues and considerations the start-up time and settling time to within 1% of the ? nal value is estimated by the following equation: t start r set ? 25 s 1k ? ? ? ? ? ? + 10 s for instance, with r set = 100k, the ltc6909 will settle to within 1% of its 1mhz ? nal value in approximately 260s. figure 7 shows the start-up time for various r set resistors. to assist in an orderly start-up sequence, the ltc6909s outputs are in a high impedance state for the ? rst 128 master clock cycles after power-up. this ensures that the ? rst clock cycle is very close to the desired operating frequency. powering up and down complex multiphase switching regulator circuits is always chaotic and can have serious s y s t e m c o n s e q u e n c e s i f i t i s n o t d o n e c a r e f u l l y. in a d d i t i o n to the ltc6909s muting of the outputs to ensure ? rst cycle accuracy, the ph0-ph1-ph2 codes 000 (all outputs are applications information 6909 f06 c1 0.1f c2 0.1f direct, low impedance connection to the v + supply v + a ltc6909 gnd ground plane ground plane ph0 ph1 out1 set ph2 mod v + d out8 r set v + a gnd c1 r set c2 ph0 ph1 out1 out2 out3 out4 set ph2 mod v + d out8 out7 out6 out5 r set ( ) 100 start-up delay (s) 1000 1k 100k 1m 10m 6909 f07 10 10k 10000 t a = 25c v + = 3v
ltc6909 16 6909f applications information high impedance) and 001 (all outputs are low) are useful for controlling the clocking of switching regulators during start-up. at start-up, most switching regulators ignore the clock input until a power good state is achieved. nearly all of linear technologys switching regulators operate in this manner. however, some switching regulators from other vendors do not ignore the clock input on start-up and yet are not synchronizable until the power good state is reached. attempting to synchronize these switching regulators before they reach the power good state can lead to problems. for these switching regulators it is best to have the ltc6909 held in the ph0-ph1-ph2 codes 000 or 001 until the switching regulator issues a power good signal. in most cases, simply connecting a switching regulators power good signal to the ph0, ph1 and /or ph2 pins accomplishes this. at most, an additional single logic inverter is required to switch from either the 000 or 001 states to any of the other six states through a power good signal. another way to use the ph0, ph1 and ph2 inputs to as- sist with power-up/down issues is to use an external part to provide a supply monitor or an undervoltage lockout (uvlo). there are several parts available that combine a comparator with a reference to ful? ll this function. the ltc6909 does not have its own internal uvlo. if the supply is below 2.7v, frequency accuracy may suffer. at a supply voltage around 2v or lower, the ltc6909 will operate erratically or will stop. it may stop randomly in a logic high or low state. figure 8 shows a circuit using an ltc1998 to monitor the supply voltage and control the logic state of the ph0 and ph1 pins. the ltc1998s threshold is set at 2.5v with 50mv of hysteresis. on power-up, as the supply ramps up, the ltc1998 holds ph0 and ph1 low, keeping the ltc6909s outputs in a high impedance state. once the supply is above 2.55v, the ltc1998 pulls the ph0 and ph1 pins high, setting the ltc6909 into the 4-phase operating mode. on power-down, the supply ramps down and the ltc1998s output goes low once the supply is below 2.45v. this puts the ltc6909s outputs in the high impedance state. all switch overs are synchronized to the ltc6909s internal oscillator to avoid glitches and runt pulses. to adjust the on/off supply voltage threshold, change the con? guration of the ltc1998. as with the power good s i g n a l , a t m o s t a n a d d i t i o n a l s i n g l e l o g i c i n v e r t e r i s r e q u i r e d to switch from either the 000 or 001 states to any of the other six states. figure 8. adding a uvlo feature to the ltc6909. in this example, the ltc6909 is in 4-phase mode for a v + > 2.5v (phx = 011) and the outputs are all high impedance for v + < 2.5v (phx = 000) ltc1998 v + batt gnd v tha 953k 49.9k 6909 f08 r set 6 5 4 battlo v logic v ha 0.1f 0.1f 0.1f 1 2 3 ltc6909 v + a gnd ph0 ph1 out1 out2 out3 out4 16 15 14 13 12 11 10 9 set ph2 mod v + d out8 out7 out6 out5 1 2 3 4 5 6 7 8
ltc6909 17 6909f typical applications 6909 ta02 *c in optional to reduce any lc ringing. not needed for low inductance plane connection v out v fb marg0 marg1 v out_lcl diffv out v osns + v osns C pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601 392k 392k 51.1k 51.1k r set 10k 22f 6.3v 470f 6.3v v out 1.5v 48a max clock sync 0 phase clock sync 90 phase 220pf margin control track/ss control track/ss control c in * 100f 25v 10f 25v 2 v in f set pgnd sgnd v out v fb marg0 marg1 v out_lcl nc3 nc2 nc1 pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601-1 v in f set pgnd sgnd 5% margin v in 10v to 14v 4.5v to 20v 120pf 22f 6.3v 10f 25v 2 0.1f 0.1f + 470f 6.3v + + v out = 0.6v r set 60.4k n + r set n = number of phases 22f 6.3v 470f 6.3v + 392k clock sync 180 phase track/ss control v out v fb marg0 marg1 v out_lcl nc3 nc2 nc1 pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601-1 v in f set pgnd sgnd 4.5v to 20v 10f 25v 2 22f 6.3v 0.1f 470f 6.3v + 392k clock sync 270 phase track/ss control v out v fb marg0 marg1 v out_lcl nc3 nc2 nc1 pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601-1 v in f set pgnd sgnd 4.5v to 20v pgood 10f 25v 2 71.5k v + a gnd ph0 ph1 out1 out2 out3 out4 set ph2 mod v + d out8 out7 out6 out5 ltc6909 ssfm disabled ssfm enabled 0.01f simply parallel multiple dc/dc module? regulator systems to achieve higher output current. board layout is as easy as copying and pasting each module regulators layout with very few external components required module is a trademark of linear technology corporation.
ltc6909 18 6909f typical applications combining eight outputs with a lowpass filter to create a sine wave using additional standard logic inverters to achieve 10- and 14-phase outputs (inverters are 74hc04 or equivalent) 14 output phases (outputs shifted by 25.71 degrees) v + v + d gnd v + a set ph0 ph1 ph2 mod out1 out2 out3 out4 out5 out6 out7 out8 0 (360) 180 51.43 231.43 102.86 282.86 154.29 334.29 205.71 25.71 257.14 77.14 308.57 128.57 6909 ta03 ltc6909 10 output phases (outputs shifted by 36 degrees) v + v + d gnd v + a set ph0 ph1 ph2 mod out1 out2 out3 out4 out5 out6 out7 out8 0 (360) 180 72 252 144 324 216 36 288 108 ltc6909 0.1f 0.1f r set 0.1f 0.1f r set ltc6909 249k 2.7v to 5.5v 0.1f 1 116 15 14 13 12 11 10 9 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 2 3 4 5 6 7 8 0.1f 0.1f 0.1f 100khz sine wave output 787k v + a gnd ph0 ph1 out1 out2 out3 out4 set ph2 mod v + d out8 out7 out6 out5 787k 402k 140k 80.6k 402k 140k 80.6k ltc1563-2 lp sa nc inva nc lpa agnd v C open 16.2k 16.2k 20k 21k v + lpb nc invb nc sb nc en 6909 ta04 500mv/div 2s/div v + = 5v thd = 0.2% 6909 ta06
ltc6909 19 6909f information furnished by linear technology corpor ation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s . package description msop (ms16) 1107 rev ? 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 12345678 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 o C 6 o typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 0.50 (.0197) bsc 4.039 p 0.102 (.159 p .004) (note 3) 0.1016 p 0.0508 (.004 p .002) 3.00 p 0.102 (.118 p .004) (note 4) 0.280 p 0.076 (.011 p .003) ref 4.90 p 0.152 (.193 p .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?)
ltc6909 20 6909f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0209 ? printed in usa part number description comments ltc1799 1khz to 33mhz thinsot? oscillator, resistor set wide frequency range ltc6900 1khz to 20mhz thinsot oscillator, resistor set low power, wide frequency range ltc6902 multiphase oscillator with spread spectrum modulation 2-, 3- or 4-phase outputs ltc6903/ltc6904 1khz to 68mhz serial port programmable oscillator 0.1% frequency resolution, i 2 c or spi interface ltc6905 17mhz to 170mhz thinsot oscillator, resistor set high frequency, 100s start-up, 7ps rms jitter ltc6905-xxx fixed frequency thinsot oscillators, up to 133mhz no trim components required ltc6906 micropower thinsot oscillator, resistor set 10khz to 1mhz, 12ma at 100khz ltc6907 micropower thinsot oscillator, resistor set 40khz to 4mhz, 36a at 400khz ltc6908-1 50khz to 10mhz dual output thinsot oscillator, resistor set complementary outputs (0/180) ltc6908-2 50khz to 10mhz dual output thinsot oscillator, resistor set quadrature outputs (0/90) ltc6930-xxx fixed frequency oscillator, 32.768khz to 8.192mhz 0.09% accuracy, 110s startup time, 105a at 32khz thinsot is a trademark of linear technology corporation. typical application related parts ltc6909 input supply 0.1f 0.1f 35.7k ltm4601 intv cc ltm4601-1 ltm4601-1 ltm4601-1 tracking s0ft-start output1 output2 output3 output4 output3 output4 output3 output4 tracking tracking v + d gnd v + a set ph0 ph1 ph2 mod out1 out2 out3 out4 out5 out6 out7 out8 ltm4601-1 ltm4601-1 ltm4601-1 ltm4601-1 tracking tracking tracking tracking 6909 ta05 providing an 8-phase synchronizing clock to ltm modules

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